=>> Building devel/lattice-ice40-examples-hx1k build started at Sat Mar 30 08:46:46 GMT 2024 port directory: /usr/ports/devel/lattice-ice40-examples-hx1k package name: lattice-ice40-examples-hx1k-g20180310_2 building for: FreeBSD pkg-builder.dan.net.uk 13.2-RELEASE-p10 FreeBSD 13.2-RELEASE-p10 amd64 maintained by: manu@FreeBSD.org Makefile datestamp: -rw-r--r-- 1 root wheel 1433 Apr 24 2023 /usr/ports/devel/lattice-ice40-examples-hx1k/Makefile Ports top last git commit: c2c35d895e Ports top unclean checkout: yes Port dir last git commit: 8d3e020ed0 Port dir unclean checkout: no Poudriere version: poudriere-git-3.4.99.20240122_1 Host OSVERSION: 1400097 Jail OSVERSION: 1302001 Job Id: 03 ---Begin Environment--- SHELL=/bin/csh OSVERSION=1302001 UNAME_v=FreeBSD 13.2-RELEASE-p10 UNAME_r=13.2-RELEASE-p10 BLOCKSIZE=K MAIL=/var/mail/root MM_CHARSET=UTF-8 LANG=C.UTF-8 STATUS=1 HOME=/root PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin MAKE_OBJDIR_CHECK_WRITABLE=0 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--CONFIGURE_ARGS-- --End CONFIGURE_ARGS-- --CONFIGURE_ENV-- MAKE=gmake XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CACHE_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.cache HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work TMPDIR="/tmp" PATH=/ccache/libexec/ccache:/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig SHELL=/bin/sh CONFIG_SHELL=/bin/sh CCACHE_DIR="/root/.ccache" --End CONFIGURE_ENV-- --MAKE_ENV-- XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work 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BSD_INSTALL_MAN="install -m 444" --End MAKE_ENV-- --PLIST_SUB-- OSREL=13.2 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib DOCSDIR="share/doc/lattice-ice40-examples-hx1k" EXAMPLESDIR="share/examples/lattice-ice40-olimex" DATADIR="share/lattice-ice40-examples-hx1k" WWWDIR="www/lattice-ice40-examples-hx1k" ETCDIR="etc/lattice-ice40-examples-hx1k" --End PLIST_SUB-- --SUB_LIST-- PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/lattice-ice40-examples-hx1k DOCSDIR=/usr/local/share/doc/lattice-ice40-examples-hx1k EXAMPLESDIR=/usr/local/share/examples/lattice-ice40-olimex WWWDIR=/usr/local/www/lattice-ice40-examples-hx1k ETCDIR=/usr/local/etc/lattice-ice40-examples-hx1k --End SUB_LIST-- ---Begin make.conf--- USE_PACKAGE_DEPENDS=yes BATCH=yes WRKDIRPREFIX=/wrkdirs PORTSDIR=/usr/ports PACKAGES=/packages DISTDIR=/distfiles FORCE_PACKAGE=yes PACKAGE_BUILDING=yes PACKAGE_BUILDING_FLAVORS=yes #### #### CCACHE_CPP2=1 WITH_SSP_PORTS=yes WITH_SSP=yes #WITH_LTO=yes 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(512-blocks, -f) unlimited data seg size (kbytes, -d) 33554432 stack size (kbytes, -s) 524288 core file size (512-blocks, -c) unlimited max memory size (kbytes, -m) unlimited locked memory (kbytes, -l) unlimited max user processes (-u) 89999 open files (-n) 8192 virtual mem size (kbytes, -v) unlimited swap limit (kbytes, -w) unlimited socket buffer size (bytes, -b) unlimited pseudo-terminals (-p) unlimited kqueues (-k) unlimited umtx shared locks (-o) unlimited --End resource limits-- =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 ===> lattice-ice40-examples-hx1k-g20180310_2 depends on file: /usr/local/sbin/pkg - not found ===> Installing existing package /packages/All/pkg-1.20.9_1.pkg [pkg-builder.dan.net.uk] Installing pkg-1.20.9_1... [pkg-builder.dan.net.uk] Extracting pkg-1.20.9_1: .......... done ===> lattice-ice40-examples-hx1k-g20180310_2 depends on file: /usr/local/sbin/pkg - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_2 =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310_2 for building ===> Extracting for lattice-ice40-examples-hx1k-g20180310_2 => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Patching for lattice-ice40-examples-hx1k-g20180310_2 =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: abc - not found ===> Installing existing package /packages/All/abc-g20220920.pkg [pkg-builder.dan.net.uk] Installing abc-g20220920... [pkg-builder.dan.net.uk] `-- Installing readline-8.2.10... [pkg-builder.dan.net.uk] | `-- Installing indexinfo-0.3.1... [pkg-builder.dan.net.uk] | `-- Extracting indexinfo-0.3.1: . done [pkg-builder.dan.net.uk] `-- Extracting readline-8.2.10: .......... done [pkg-builder.dan.net.uk] Extracting abc-g20220920: .. done ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: abc - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_2 ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: arachne-pnr - not found ===> Installing existing package /packages/All/arachne-pnr-g20181021_3.pkg [pkg-builder.dan.net.uk] Installing arachne-pnr-g20181021_3... [pkg-builder.dan.net.uk] Extracting arachne-pnr-g20181021_3: ...... done ===== Message from arachne-pnr-g20181021_3: -- ===> NOTICE: The arachne-pnr port currently does not have a maintainer. As a result, it is more likely to have unresolved issues, not be up-to-date, or even be removed in the future. To volunteer to maintain this port, please create an issue at: https://bugs.freebsd.org/bugzilla More information about port maintainership is available at: https://docs.freebsd.org/en/articles/contributing/#ports-contributing ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: arachne-pnr - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_2 ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: icepack - not found ===> Installing existing package /packages/All/icestorm-g20231212.pkg [pkg-builder.dan.net.uk] Installing icestorm-g20231212... [pkg-builder.dan.net.uk] `-- Installing libftdi1-1.5_4... [pkg-builder.dan.net.uk] | `-- Installing boost-libs-1.84.0... [pkg-builder.dan.net.uk] | | `-- Installing icu-74.2,1... [pkg-builder.dan.net.uk] | | `-- Extracting icu-74.2,1: .......... done [pkg-builder.dan.net.uk] | `-- Extracting boost-libs-1.84.0: .......... done [pkg-builder.dan.net.uk] | `-- Installing gettext-runtime-0.22.3_1... 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[pkg-builder.dan.net.uk] `-- Extracting py39-boost-libs-1.84.0: .......... done [pkg-builder.dan.net.uk] Extracting icestorm-g20231212: .......... done ===== Message from boost-libs-1.84.0: -- You have built the Boost library with thread support. Don't forget to add -pthread to your linker options when linking your code. ===== Message from python39-3.9.18_1: -- Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: py39-gdbm databases/py-gdbm@py39 py39-sqlite3 databases/py-sqlite3@py39 py39-tkinter x11-toolkits/py-tkinter@py39 ===== Message from py39-boost-libs-1.84.0: -- You have built the Boost library with thread support. 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[pkg-builder.dan.net.uk] | | `-- Installing encodings-1.1.0,1... [pkg-builder.dan.net.uk] | | `-- Extracting encodings-1.1.0,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing fribidi-1.0.13_1... [pkg-builder.dan.net.uk] | | `-- Extracting fribidi-1.0.13_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libXft-2.3.7_1... [pkg-builder.dan.net.uk] | | `-- Extracting libXft-2.3.7_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libthai-0.1.29_1... [pkg-builder.dan.net.uk] | | | `-- Installing libdatrie-0.2.13_2... [pkg-builder.dan.net.uk] | | | `-- Extracting libdatrie-0.2.13_2: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting libthai-0.1.29_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing xorg-fonts-truetype-7.7_1... [pkg-builder.dan.net.uk] | | | `-- Installing dejavu-2.37_3... [pkg-builder.dan.net.uk] | | | `-- Installing mkfontscale-1.2.3... [pkg-builder.dan.net.uk] | | | | `-- Installing libfontenc-1.1.8... [pkg-builder.dan.net.uk] | | | | `-- Extracting libfontenc-1.1.8: ...... done [pkg-builder.dan.net.uk] | | | `-- Extracting mkfontscale-1.2.3: .... done [pkg-builder.dan.net.uk] | | | `-- Extracting dejavu-2.37_3: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing font-bh-ttf-1.0.3_5... [pkg-builder.dan.net.uk] | | | `-- Extracting font-bh-ttf-1.0.3_5: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing font-misc-ethiopic-1.0.4... [pkg-builder.dan.net.uk] | | | `-- Extracting font-misc-ethiopic-1.0.4: ... done [pkg-builder.dan.net.uk] | | | `-- Installing font-misc-meltho-1.0.3_5... [pkg-builder.dan.net.uk] | | | `-- Extracting font-misc-meltho-1.0.3_5: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting pango-1.50.14: .......... done [pkg-builder.dan.net.uk] | `-- Extracting graphviz-9.0.0_3: .......... done [pkg-builder.dan.net.uk] | `-- Installing gtk3-3.24.41... [pkg-builder.dan.net.uk] | | `-- Installing adwaita-icon-theme-42.0... [pkg-builder.dan.net.uk] | | `-- Installing gdk-pixbuf2-2.42.10_2... [pkg-builder.dan.net.uk] | | | `-- Installing libxml2-2.11.7... [pkg-builder.dan.net.uk] | | | `-- Extracting libxml2-2.11.7: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing shared-mime-info-2.2_2... [pkg-builder.dan.net.uk] | | | `-- Extracting shared-mime-info-2.2_2: ......... done [pkg-builder.dan.net.uk] | | `-- Extracting gdk-pixbuf2-2.42.10_2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing gtk-update-icon-cache-3.24.31_1... [pkg-builder.dan.net.uk] | | `-- Extracting gtk-update-icon-cache-3.24.31_1: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting adwaita-icon-theme-42.0: .......... done [pkg-builder.dan.net.uk] | | `-- Installing colord-1.4.7... [pkg-builder.dan.net.uk] | | `-- Installing hwdata-0.380,1... [pkg-builder.dan.net.uk] | | `-- Extracting hwdata-0.380,1: ...... done [pkg-builder.dan.net.uk] | | `-- Installing lcms2-2.16_1... [pkg-builder.dan.net.uk] | | `-- Extracting lcms2-2.16_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libgudev-237... [pkg-builder.dan.net.uk] | | | `-- Installing libudev-devd-0.5.2... [pkg-builder.dan.net.uk] | | | `-- Extracting libudev-devd-0.5.2: ..... done [pkg-builder.dan.net.uk] | | `-- Extracting libgudev-237: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libgusb-0.3.10_1... [pkg-builder.dan.net.uk] | | `-- Extracting libgusb-0.3.10_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing polkit-124_2... [pkg-builder.dan.net.uk] | | | `-- Installing duktape-lib-2.7.0... [pkg-builder.dan.net.uk] | | | `-- Extracting duktape-lib-2.7.0: ...... done ===> Creating groups. Creating group 'polkitd' with gid '565'. ===> Creating users Creating user 'polkitd' with uid '565'. [pkg-builder.dan.net.uk] | | `-- Extracting polkit-124_2: ......... done [pkg-builder.dan.net.uk] | | `-- Installing sqlite3-3.45.1,1... [pkg-builder.dan.net.uk] | | | `-- Installing libedit-3.1.20230828_1,1... [pkg-builder.dan.net.uk] | | | `-- Extracting libedit-3.1.20230828_1,1: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting sqlite3-3.45.1,1: ......... done ===> Creating groups. Creating group 'colord' with gid '970'. ===> Creating users Creating user 'colord' with uid '970'. [pkg-builder.dan.net.uk] | | `-- Extracting colord-1.4.7: .......... done [pkg-builder.dan.net.uk] | | `-- Installing cups-2.4.7_2... [pkg-builder.dan.net.uk] | | `-- Installing avahi-app-0.8_2... [pkg-builder.dan.net.uk] | | | `-- Installing dbus-glib-0.112_1... [pkg-builder.dan.net.uk] | | | `-- Extracting dbus-glib-0.112_1: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing gdbm-1.23... [pkg-builder.dan.net.uk] | | | `-- Extracting gdbm-1.23: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing gnome_subr-1.0... [pkg-builder.dan.net.uk] | | | `-- Extracting gnome_subr-1.0: . done [pkg-builder.dan.net.uk] | | | `-- Installing libdaemon-0.14_1... [pkg-builder.dan.net.uk] | | | `-- Extracting libdaemon-0.14_1: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing libevent-2.1.12... [pkg-builder.dan.net.uk] | | | `-- Extracting libevent-2.1.12: .......... done ===> Creating groups. Creating group 'avahi' with gid '558'. ===> Creating users Creating user 'avahi' with uid '558'. [pkg-builder.dan.net.uk] | | `-- Extracting avahi-app-0.8_2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing gnutls-3.7.10_2... [pkg-builder.dan.net.uk] | | | `-- Installing gmp-6.3.0... [pkg-builder.dan.net.uk] | | | `-- Extracting gmp-6.3.0: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing libidn2-2.3.7... [pkg-builder.dan.net.uk] | | | `-- Installing libunistring-1.2... [pkg-builder.dan.net.uk] | | | `-- Extracting libunistring-1.2: .......... done [pkg-builder.dan.net.uk] | | | `-- Extracting libidn2-2.3.7: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing libtasn1-4.19.0_1... [pkg-builder.dan.net.uk] | | | `-- Extracting libtasn1-4.19.0_1: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing nettle-3.9.1... [pkg-builder.dan.net.uk] | | | `-- Extracting nettle-3.9.1: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing p11-kit-0.25.3_1... [pkg-builder.dan.net.uk] | | | `-- Extracting p11-kit-0.25.3_1: .......... done [pkg-builder.dan.net.uk] | | | `-- Installing unbound-1.19.3... [pkg-builder.dan.net.uk] | | | `-- Installing libnghttp2-1.60.0... [pkg-builder.dan.net.uk] | | | `-- Extracting libnghttp2-1.60.0: ....... done ===> Creating groups. Using existing group 'unbound'. ===> Creating users Using existing user 'unbound'. [pkg-builder.dan.net.uk] | | | `-- Extracting unbound-1.19.3: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting gnutls-3.7.10_2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libpaper-1.1.28_1... [pkg-builder.dan.net.uk] | | `-- Extracting libpaper-1.1.28_1: .......... done ===> Creating groups. Creating group 'cups' with gid '193'. ===> Creating users Creating user 'cups' with uid '193'. [pkg-builder.dan.net.uk] | | `-- Extracting cups-2.4.7_2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing gsettings-desktop-schemas-42.0... [pkg-builder.dan.net.uk] | | `-- Extracting gsettings-desktop-schemas-42.0: .......... done [pkg-builder.dan.net.uk] | | `-- Installing hicolor-icon-theme-0.17... [pkg-builder.dan.net.uk] | | `-- Extracting hicolor-icon-theme-0.17: . done [pkg-builder.dan.net.uk] | | `-- Installing libXcomposite-0.4.6_1,1... [pkg-builder.dan.net.uk] | | `-- Extracting libXcomposite-0.4.6_1,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libXcursor-1.2.2... [pkg-builder.dan.net.uk] | | `-- Extracting libXcursor-1.2.2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libXdamage-1.1.6... [pkg-builder.dan.net.uk] | | `-- Extracting libXdamage-1.1.6: ...... done [pkg-builder.dan.net.uk] | | `-- Installing libXinerama-1.1.4_3,1... [pkg-builder.dan.net.uk] | | `-- Extracting libXinerama-1.1.4_3,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libepoxy-1.5.9... [pkg-builder.dan.net.uk] | | `-- Extracting libepoxy-1.5.9: .......... done [pkg-builder.dan.net.uk] | | `-- Installing librsvg2-rust-2.56.4_5... [pkg-builder.dan.net.uk] | | `-- Extracting librsvg2-rust-2.56.4_5: .......... done [pkg-builder.dan.net.uk] | | `-- Installing libxkbcommon-1.6.0_2... [pkg-builder.dan.net.uk] | | `-- Installing wayland-1.22.0... [pkg-builder.dan.net.uk] | | | `-- Installing libepoll-shim-0.0.20230411... [pkg-builder.dan.net.uk] | | | `-- Extracting libepoll-shim-0.0.20230411: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting wayland-1.22.0: .......... done [pkg-builder.dan.net.uk] | | `-- Installing xkeyboard-config-2.41_4... [pkg-builder.dan.net.uk] | | `-- Extracting xkeyboard-config-2.41_4: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting libxkbcommon-1.6.0_2: .......... done [pkg-builder.dan.net.uk] | `-- Extracting gtk3-3.24.41: .......... done [pkg-builder.dan.net.uk] | `-- Installing py39-gobject3-3.42.2... [pkg-builder.dan.net.uk] | | `-- Installing gobject-introspection-1.78.1_2,1... [pkg-builder.dan.net.uk] | | `-- Extracting gobject-introspection-1.78.1_2,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing py39-cairo-1.21.0,1... [pkg-builder.dan.net.uk] | | `-- Extracting py39-cairo-1.21.0,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing pygobject3-common-3.42.2... [pkg-builder.dan.net.uk] | | `-- Extracting pygobject3-common-3.42.2: .. done [pkg-builder.dan.net.uk] | `-- Extracting py39-gobject3-3.42.2: .......... done [pkg-builder.dan.net.uk] | `-- Installing py39-numpy-1.25.0_6,1... [pkg-builder.dan.net.uk] | | `-- Installing gcc13-13.2.0_4... [pkg-builder.dan.net.uk] | | `-- Installing binutils-2.40_5,1... [pkg-builder.dan.net.uk] | | `-- Extracting binutils-2.40_5,1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing mpc-1.3.1_1... [pkg-builder.dan.net.uk] | | | `-- Installing mpfr-4.2.1,1... [pkg-builder.dan.net.uk] | | | `-- Extracting mpfr-4.2.1,1: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting mpc-1.3.1_1: ...... done [pkg-builder.dan.net.uk] | | `-- Extracting gcc13-13.2.0_4: .......... done create symlink for gcc13 create symlink for gcc13 (world) create symlink for g++13 create symlink for g++13 (world) create symlink for cpp13 create symlink for cpp13 (world) [pkg-builder.dan.net.uk] | | `-- Installing openblas-0.3.25,2... [pkg-builder.dan.net.uk] | | `-- Extracting openblas-0.3.25,2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing py39-setuptools-63.1.0_1... [pkg-builder.dan.net.uk] | | `-- Extracting py39-setuptools-63.1.0_1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing suitesparse-umfpack-6.3.2... [pkg-builder.dan.net.uk] | | `-- Installing suitesparse-amd-3.3.1... [pkg-builder.dan.net.uk] | | | `-- Installing suitesparse-config-7.6.1... [pkg-builder.dan.net.uk] | | | `-- Extracting suitesparse-config-7.6.1: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting suitesparse-amd-3.3.1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing suitesparse-camd-3.3.1... [pkg-builder.dan.net.uk] | | `-- Extracting suitesparse-camd-3.3.1: .......... done [pkg-builder.dan.net.uk] | | `-- Installing suitesparse-ccolamd-3.3.2... [pkg-builder.dan.net.uk] | | `-- Extracting suitesparse-ccolamd-3.3.2: .......... done [pkg-builder.dan.net.uk] | | `-- Installing suitesparse-cholmod-5.2.0... [pkg-builder.dan.net.uk] | | | `-- Installing suitesparse-colamd-3.3.2... [pkg-builder.dan.net.uk] | | | `-- Extracting suitesparse-colamd-3.3.2: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting suitesparse-cholmod-5.2.0: .......... done [pkg-builder.dan.net.uk] | | `-- Extracting suitesparse-umfpack-6.3.2: .......... done [pkg-builder.dan.net.uk] | `-- Extracting py39-numpy-1.25.0_6,1: .......... done [pkg-builder.dan.net.uk] `-- Extracting py39-xdot-1.2_4: .......... done [pkg-builder.dan.net.uk] `-- Installing tcl86-8.6.14_1... [pkg-builder.dan.net.uk] `-- Extracting tcl86-8.6.14_1: .......... done [pkg-builder.dan.net.uk] `-- Installing yices-2.6.4... [pkg-builder.dan.net.uk] `-- Extracting yices-2.6.4: .......... done [pkg-builder.dan.net.uk] Extracting yosys-0.39: .......... done ==> Running trigger: fontconfig.ucl Running fc-cache to build fontconfig cache... ==> Running trigger: gdk-pixbuf-query-loaders.ucl Generating gdk-pixbuf modules cache ==> Running trigger: gio-modules.ucl Generating GIO modules cache ==> Running trigger: gtk-update-icon-cache.ucl Generating GTK icon cache for /usr/local/share/icons/hicolor Generating GTK icon cache for /usr/local/share/icons/Adwaita ==> Running trigger: glib-schemas.ucl Compiling glib schemas ==> Running trigger: shared-mime-info.ucl Building the Shared MIME-Info database cache ===== Message from freetype2-2.13.2: -- The 2.7.x series now uses the new subpixel hinting mode (V40 port's option) as the default, emulating a modern version of ClearType. This change inevitably leads to different rendering results, and you might change port's options to adapt it to your taste (or use the new "FREETYPE_PROPERTIES" environment variable). The environment variable "FREETYPE_PROPERTIES" can be used to control the driver properties. Example: FREETYPE_PROPERTIES=truetype:interpreter-version=35 \ cff:no-stem-darkening=1 \ autofitter:warping=1 This allows to select, say, the subpixel hinting mode at runtime for a given application. If LONG_PCF_NAMES port's option was enabled, the PCF family names may include the foundry and information whether they contain wide characters. For example, "Sony Fixed" or "Misc Fixed Wide", instead of "Fixed". This can be disabled at run time with using pcf:no-long-family-names property, if needed. Example: FREETYPE_PROPERTIES=pcf:no-long-family-names=1 How to recreate fontconfig cache with using such environment variable, if needed: # env FREETYPE_PROPERTIES=pcf:no-long-family-names=1 fc-cache -fsv The controllable properties are listed in the section "Controlling FreeType Modules" in the reference's table of contents (/usr/local/share/doc/freetype2/reference/index.html, if documentation was installed). ===== Message from freeglut-3.2.1: -- Joystick support is untested and it is unknown if it works. Do not hesitate to contact x11@FreeBSD.org if this causes issues. ===== Message from dejavu-2.37_3: -- Make sure that the freetype module is loaded. If it is not, add the following line to the "Modules" section of your X Windows configuration file: Load "freetype" Add the following line to the "Files" section of X Windows configuration file: FontPath "/usr/local/share/fonts/dejavu/" Note: your X Windows configuration file is typically /etc/X11/XF86Config if you are using XFree86, and /etc/X11/xorg.conf if you are using X.Org. ===== Message from duktape-lib-2.7.0: -- ===> NOTICE: The duktape-lib port currently does not have a maintainer. As a result, it is more likely to have unresolved issues, not be up-to-date, or even be removed in the future. To volunteer to maintain this port, please create an issue at: https://bugs.freebsd.org/bugzilla More information about port maintainership is available at: https://docs.freebsd.org/en/articles/contributing/#ports-contributing ===== Message from wayland-1.22.0: -- Wayland requires XDG_RUNTIME_DIR to be defined to a path that will contain "wayland-%d" unix(4) sockets. This is usually handled by consolekit2 (via ck-launch-session) or pam_xdg (via login). ===== Message from libxkbcommon-1.6.0_2: -- If arrow keys don't work under X11 switch to legacy rules e.g., For sh/bash/ksh/zsh run and (optionally) add into ~/.profile: export XKB_DEFAULT_RULES=xorg For csh/tcsh run and (optionally) add into ~/.login: setenv XKB_DEFAULT_RULES xorg ===== Message from gcc13-13.2.0_4: -- To ensure binaries built with this toolchain find appropriate versions of the necessary run-time libraries, you may want to link using -Wl,-rpath=/usr/local/lib/gcc13 For ports leveraging USE_GCC, USES=compiler, or USES=fortran this happens transparently. ===> lattice-ice40-examples-hx1k-g20180310_2 depends on executable: yosys - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_2 ===> lattice-ice40-examples-hx1k-g20180310_2 depends on package: gmake>=4.4.1 - not found ===> Installing existing package /packages/All/gmake-4.4.1.pkg [pkg-builder.dan.net.uk] Installing gmake-4.4.1... [pkg-builder.dan.net.uk] Extracting gmake-4.4.1: .......... done ===> lattice-ice40-examples-hx1k-g20180310_2 depends on package: gmake>=4.4.1 - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310_2 =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Configuring for lattice-ice40-examples-hx1k-g20180310_2 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Building for lattice-ice40-examples-hx1k-g20180310_2 /usr/bin/env -i HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work PWD="${PWD}" OSVERSION=1302001 PATH=/ccache/libexec/ccache:/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin TMPDIR=/tmp UNAME_r=13.2-RELEASE-p10 UNAME_v=FreeBSD\ 13.2-RELEASE-p10 XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CACHE_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.cache HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work TMPDIR="/tmp" PATH=/ccache/libexec/ccache:/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES PREFIX=/usr/local LOCALBASE=/usr/local CC="cc" CFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" -fstack-protector-strong " LIBS="" CXX="c++" CXXFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CCACHE_DIR="/root/.ccache" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -C /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb gmake: Entering directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.39 (git sha1 00338082b00, c++ 14.0.5 -O2 -fstack-protector-strong -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: example.v Parsing Verilog input from `example.v' to AST representation. Storing AST representation for module `$abstract\top'. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. Generating RTLIL representation for module `\top'. 2.3.1. Analyzing design hierarchy.. Top module: \top 2.3.2. Analyzing design hierarchy.. Top module: \top Removing unused module `$abstract\top'. Removed 1 unused modules. 2.4. Executing PROC pass (convert processes to netlists). 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. Removed a total of 0 dead cases. 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 29 assignments to connections. 2.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Set init value: \Q = 1'0 Found init rule in `\top.$proc$example.v:23$400'. Set init value: \mode = 1'1 Found init rule in `\top.$proc$example.v:22$399'. Set init value: \rst_cnt = 15'000000000000000 2.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Found async reset \R in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Found async reset \S in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Found async reset \R in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Found async reset \S in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Found async reset \R in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Found async reset \S in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. Found async reset \R in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. Creating decoders for process `\top.$proc$example.v:23$400'. Creating decoders for process `\top.$proc$example.v:22$399'. Creating decoders for process `\top.$proc$example.v:38$385'. 1/5: $0\cntr[14:0] 2/5: $0\mode[0:0] 3/5: $0\rst_cnt[14:0] 4/5: $0\LED2_m1_r[0:0] 5/5: $0\LED1_m1_r[0:0] Creating decoders for process `\top.$proc$example.v:34$383'. 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. created $adff cell `$procdff$461' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. created $dff cell `$procdff$462' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. created $adff cell `$procdff$463' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. created $dff cell `$procdff$464' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. created $adff cell `$procdff$465' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. created $dff cell `$procdff$466' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. created $adff cell `$procdff$467' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. created $dff cell `$procdff$468' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. created $dff cell `$procdff$469' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. created $dff cell `$procdff$470' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. created $adff cell `$procdff$471' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. created $dff cell `$procdff$472' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. created $adff cell `$procdff$473' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. created $dff cell `$procdff$474' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. created $adff cell `$procdff$475' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. created $dff cell `$procdff$476' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. created $adff cell `$procdff$477' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. created $dff cell `$procdff$478' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. created $dff cell `$procdff$479' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. created $dff cell `$procdff$480' with positive edge clock. Creating register for signal `\top.\BUT1_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$481' with positive edge clock. Creating register for signal `\top.\BUT2_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$482' with positive edge clock. Creating register for signal `\top.\LED1_m0_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$483' with positive edge clock. Creating register for signal `\top.\LED2_m0_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$484' with positive edge clock. Creating register for signal `\top.\LED1_m1_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$485' with positive edge clock. Creating register for signal `\top.\LED2_m1_r' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$486' with positive edge clock. Creating register for signal `\top.\cntr' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$487' with positive edge clock. Creating register for signal `\top.\rst_cnt' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$488' with positive edge clock. Creating register for signal `\top.\mode' using process `\top.$proc$example.v:38$385'. created $dff cell `$procdff$489' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:34$383'. created $dff cell `$procdff$490' with positive edge clock. 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. Removing empty process `top.$proc$example.v:23$400'. Removing empty process `top.$proc$example.v:22$399'. Found and cleaned up 4 empty switches in `\top.$proc$example.v:38$385'. Removing empty process `top.$proc$example.v:38$385'. Removing empty process `top.$proc$example.v:34$383'. Cleaned up 22 empty switches. 2.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.5. Executing FLATTEN pass (flatten design). 2.6. Executing TRIBUF pass. 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 2.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 25 unused wires. 2.10. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $procmux$449: \rst_cnt -> { 1'1 \rst_cnt [13:0] } Analyzing evaluation results. Removed 0 multiplexer ports. 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. 2.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.11.9. Rerunning OPT passes. (Maybe there is more to do..) 2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.11.13. Executing OPT_DFF pass (perform DFF optimizations). 2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.11.16. Finished OPT passes. (There is nothing left to do.) 2.12. Executing FSM pass (extract and optimize FSM). 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.13. Executing OPT pass (performing simple optimizations). 2.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $procdff$489 ($dff) from module top (D = $auto$rtlil.cc:2485:Not$492, Q = \mode). Adding SRST signal on $procdff$488 ($dff) from module top (D = $procmux$449_Y, Q = \rst_cnt, rval = 15'000000000000000). Adding EN signal on $auto$ff.cc:266:slice$494 ($sdff) from module top (D = $add$example.v:44$388_Y [13:0], Q = \rst_cnt [13:0]). Adding SRST signal on $procdff$487 ($dff) from module top (D = $add$example.v:41$386_Y, Q = \cntr, rval = 15'000000000000000). Adding SRST signal on $procdff$486 ($dff) from module top (D = $procmux$453_Y, Q = \LED2_m1_r, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$498 ($sdff) from module top (D = 1'1, Q = \LED2_m1_r). Adding SRST signal on $procdff$485 ($dff) from module top (D = $procmux$457_Y, Q = \LED1_m1_r, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$500 ($sdff) from module top (D = 1'0, Q = \LED1_m1_r). 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. 2.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.13.9. Rerunning OPT passes. (Maybe there is more to do..) 2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.13.13. Executing OPT_DFF pass (perform DFF optimizations). 2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.13.16. Finished OPT passes. (There is nothing left to do.) 2.14. Executing WREDUCE pass (reducing word size of cells). Removed top 11 bits (of 12) from port B of cell top.$add$example.v:35$384 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:41$386 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:44$388 ($add). Removed top 1 bits (of 15) from port B of cell top.$eq$example.v:55$397 ($eq). 2.15. Executing PEEPOPT pass (run peephole optimizers). 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.17. Executing SHARE pass (SAT-based resource sharing). 2.18. Executing TECHMAP pass (map to technology primitives). 2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.18.2. Continuing TECHMAP pass. No more expansions possible. 2.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.21. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:35$384 ($add). creating $macc model for $add$example.v:41$386 ($add). creating $macc model for $add$example.v:44$388 ($add). creating $alu model for $macc $add$example.v:44$388. creating $alu model for $macc $add$example.v:41$386. creating $alu model for $macc $add$example.v:35$384. creating $alu model for $gt$example.v:59$398 ($gt): new $alu creating $alu cell for $gt$example.v:59$398: $auto$alumacc.cc:485:replace_alu$504 creating $alu cell for $add$example.v:35$384: $auto$alumacc.cc:485:replace_alu$515 creating $alu cell for $add$example.v:41$386: $auto$alumacc.cc:485:replace_alu$518 creating $alu cell for $add$example.v:44$388: $auto$alumacc.cc:485:replace_alu$521 created 4 $alu and 0 $macc cells. 2.22. Executing OPT pass (performing simple optimizations). 2.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.22.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 2 unused wires. 2.22.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.22.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.22.16. Finished OPT passes. (There is nothing left to do.) 2.23. Executing MEMORY pass. 2.23.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.26. Executing TECHMAP pass (map to technology primitives). 2.26.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K_'. Successfully finished Verilog frontend. 2.26.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/spram_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/spram_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_SPRAM_'. Successfully finished Verilog frontend. 2.26.3. Continuing TECHMAP pass. No more expansions possible. 2.27. Executing ICE40_BRAMINIT pass. 2.28. Executing OPT pass (performing simple optimizations). 2.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. 2.28.5. Finished fast OPT passes. 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.30. Executing OPT pass (performing simple optimizations). 2.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.30.9. Finished OPT passes. (There is nothing left to do.) 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 2.32. Executing TECHMAP pass (map to technology primitives). 2.32.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.32.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$091610cd349a68bd5539cffd7126f0d76e9bca00\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $eq. Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.33. Executing OPT pass (performing simple optimizations). 2.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 18 cells. 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 46 unused cells and 76 unused wires. 2.33.5. Finished fast OPT passes. 2.34. Executing ICE40_OPT pass (performing simple optimizations). 2.34.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$504.slice[0].carry: CO=\cntr [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry: CO=\clk_div [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry: CO=\cntr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry: CO=\rst_cnt [0] 2.34.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.34.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 0 unused wires. 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 2.34.7. Running ICE40 specific optimizations. 2.34.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.34.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.34.12. Finished OPT passes. (There is nothing left to do.) 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.36. Executing TECHMAP pass (map to technology primitives). 2.36.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.36.2. Continuing TECHMAP pass. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. No more expansions possible. 2.37. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$515.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$518.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$521.slice[0].carry ($lut). 2.39. Executing ICE40_OPT pass (performing simple optimizations). 2.39.1. Running ICE40 specific optimizations. 2.39.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 46 cells. 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 303 unused wires. 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 2.39.7. Running ICE40 specific optimizations. 2.39.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.39.12. Finished OPT passes. (There is nothing left to do.) 2.40. Executing TECHMAP pass (map to technology primitives). 2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.40.2. Continuing TECHMAP pass. No more expansions possible. 2.41. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/abc9_model.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'. Successfully finished Verilog frontend. 2.42. Executing ABC9 pass. 2.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module top. Found 0 SCCs. 2.42.4. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.5. Executing PROC pass (convert processes to netlists). 2.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.42.5.4. Executing PROC_INIT pass (extract init attributes). 2.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 2.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.42.5.12. Executing OPT_EXPR pass (perform const folding). 2.42.6. Executing TECHMAP pass (map to technology primitives). 2.42.6.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.42.6.2. Continuing TECHMAP pass. No more expansions possible. 2.42.7. Executing OPT pass (performing simple optimizations). 2.42.7.1. Executing OPT_EXPR pass (perform const folding). 2.42.7.2. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.42.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Removed 0 multiplexer ports. 2.42.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Performed a total of 0 changes. 2.42.7.5. Executing OPT_MERGE pass (detect identical cells). Removed a total of 0 cells. 2.42.7.6. Executing OPT_DFF pass (perform DFF optimizations). 2.42.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2.42.7.8. Executing OPT_EXPR pass (perform const folding). 2.42.7.9. Finished OPT passes. (There is nothing left to do.) 2.42.8. Executing TECHMAP pass (map to technology primitives). 2.42.8.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/abc9_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 2.42.8.2. Continuing TECHMAP pass. No more expansions possible. 2.42.9. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/abc9_model.v Parsing Verilog input from `/usr/local/bin/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 2.42.10. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.11. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.13. Executing TECHMAP pass (map to technology primitives). 2.42.13.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.42.13.2. Continuing TECHMAP pass. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4. Using template SB_CARRY for cells of type SB_CARRY. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. No more expansions possible. 2.42.14. Executing OPT pass (performing simple optimizations). 2.42.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.42.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 12 cells. 2.42.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.42.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.42.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.42.14.6. Executing OPT_DFF pass (perform DFF optimizations). 2.42.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 24 unused wires. 2.42.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.42.14.9. Rerunning OPT passes. (Maybe there is more to do..) 2.42.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.42.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.42.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.42.14.13. Executing OPT_DFF pass (perform DFF optimizations). 2.42.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.42.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.42.14.16. Finished OPT passes. (There is nothing left to do.) 2.42.15. Executing AIGMAP pass (map logic to AIG). Module top: replaced 7 cells with 43 new cells, skipped 11 cells. replaced 2 cell types: 2 $_OR_ 5 $_MUX_ not replaced 3 cell types: 8 $specify2 1 $_NOT_ 2 $_AND_ 2.42.16. Executing AIGMAP pass (map logic to AIG). Module top: replaced 19 cells with 80 new cells, skipped 219 cells. replaced 3 cell types: 16 $_OR_ 1 $_ANDNOT_ 2 $_MUX_ not replaced 10 cell types: 20 $_NOT_ 17 $_AND_ 16 SB_DFF 1 SB_DFFE 16 SB_DFFSR 15 SB_DFFESR 1 SB_DFFESS 52 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 49 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101 32 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011 2.42.16.1. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.16.2. Executing ABC9_OPS pass (helper functions for ABC9). 2.42.16.3. Executing XAIGER backend. Extracted 40 AND gates and 359 wires from module `top' to a netlist network with 52 inputs and 87 outputs. 2.42.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). 2.42.16.5. Executing ABC9. Running ABC command: "abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_lut /input.lut ABC: + read_box /input.box ABC: + &read /input.xaig ABC: + &ps ABC: /input : i/o = 52/ 87 and = 36 lev = 6 (0.31) mem = 0.01 MB box = 133 bb = 81 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: /input : i/o = 52/ 87 and = 68 lev = 6 (0.31) mem = 0.01 MB ch = 10 box = 133 bb = 81 ABC: + &if -W 250 -v ABC: K = 4. Memory (bytes): Truth = 0. Cut = 48. Obj = 128. Set = 528. CutMin = no ABC: Node = 68. Ch = 9. Total mem = 0.10 MB. Peak cut mem = 0.00 MB. ABC: P: Del = 3186.00. Ar = 16.0. Edge = 53. Cut = 253. T = 0.00 sec ABC: P: Del = 3186.00. Ar = 19.0. Edge = 64. Cut = 250. T = 0.00 sec ABC: P: Del = 3186.00. Ar = 19.0. Edge = 64. Cut = 254. T = 0.00 sec ABC: F: Del = 3186.00. Ar = 18.0. Edge = 61. Cut = 251. T = 0.00 sec ABC: A: Del = 3186.00. Ar = 17.0. Edge = 52. Cut = 245. T = 0.00 sec ABC: A: Del = 3186.00. Ar = 17.0. Edge = 52. Cut = 192. T = 0.00 sec ABC: Total time = 0.00 sec ABC: + &write -n /output.aig ABC: + &mfs ABC: + &ps -l ABC: /input : i/o = 52/ 87 and = 29 lev = 5 (0.22) mem = 0.01 MB box = 133 bb = 81 ABC: Mapping (K=4) : lut = 15 edge = 42 lev = 4 (0.18) levB = 16 mem = 0.00 MB ABC: LUT = 15 : 2=6 40.0 % 3=6 40.0 % 4=3 20.0 % Ave = 2.80 ABC: + &write -n /output.aig ABC: + time ABC: elapse: 0.02 seconds, total: 0.02 seconds 2.42.16.6. Executing AIGER frontend. Removed 34 unused cells and 699 unused wires. 2.42.16.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 21 ABC RESULTS: $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells: 52 ABC RESULTS: input signals: 13 ABC RESULTS: output signals: 87 Removing temp directory. 2.42.17. Executing TECHMAP pass (map to technology primitives). 2.42.17.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/abc9_unmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 2.42.17.2. Continuing TECHMAP pass. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. No more expansions possible. 2.43. Executing ICE40_WRAPCARRY pass (wrap carries). 2.44. Executing TECHMAP pass (map to technology primitives). 2.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.44.2. Continuing TECHMAP pass. No more expansions possible. Removed 19 unused cells and 727 unused wires. 2.45. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 60 1-LUT 6 2-LUT 9 3-LUT 42 4-LUT 3 with \SB_CARRY (#0) 36 with \SB_CARRY (#1) 36 Eliminating LUTs. Number of LUTs: 60 1-LUT 6 2-LUT 9 3-LUT 42 4-LUT 3 with \SB_CARRY (#0) 36 with \SB_CARRY (#1) 36 Combining LUTs. Number of LUTs: 59 1-LUT 6 2-LUT 8 3-LUT 42 4-LUT 3 with \SB_CARRY (#0) 36 with \SB_CARRY (#1) 36 Eliminated 0 LUTs. Combined 1 LUTs. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. Using template $paramod$d151c38cd9b2f723ca2e7bae80e30ea6d32d7878\$lut for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. No more expansions possible. Removed 0 unused cells and 123 unused wires. 2.47. Executing AUTONAME pass. Renamed 973 objects in module top (38 iterations). 2.48. Executing HIERARCHY pass (managing design hierarchy). 2.48.1. Analyzing design hierarchy.. Top module: \top 2.48.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.49. Printing statistics. === top === Number of wires: 119 Number of wire bits: 170 Number of public wires: 119 Number of public wire bits: 170 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 157 SB_CARRY 49 SB_DFF 16 SB_DFFE 1 SB_DFFESR 15 SB_DFFESS 1 SB_DFFSR 16 SB_LUT4 59 2.50. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 2.51. Executing BLIF backend. End of script. Logfile hash: 0a58969053, CPU: user 1.34s system 0.01s, MEM: 33.80 MB peak Yosys 0.39 (git sha1 00338082b00, c++ 14.0.5 -O2 -fstack-protector-strong -fno-strict-aliasing -fPIC -Os) Time spent: 58% 21x read_verilog (0 sec), 6% 11x techmap (0 sec), ... arachne-pnr -d 1k -o example.asc -p ice40hx1k-evb.pcf example.blif -P vq100 seed: 1 device: 1k read_chipdb +/share/arachne-pnr/chipdb-1k.bin... supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100 read_blif example.blif... prune... read_pcf ice40hx1k-evb.pcf... instantiate_io... pack... After packing: IOs 5 / 72 GBs 0 / 8 GB_IOs 0 / 8 LCs 85 / 1280 DFF 16 CARRY 20 CARRY, DFF 33 DFF PASS 4 CARRY PASS 6 BRAMs 0 / 16 WARMBOOTs 0 / 1 PLLs 0 / 0 place_constraints... promote_globals... promoted clk_24KHz, 38 / 38 promoted LED1_m1_r_SB_DFFESS_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O, 17 / 17 promoted BUT2_r_SB_LUT4_I2_O[1], 16 / 17 promoted reset_SB_LUT4_I2_1_O, 14 / 14 promoted CLK$2, 12 / 12 promoted 5 nets 2 sr/we 1 cen/wclke 2 clk 5 globals 2 sr/we 1 cen/wclke 2 clk realize_constants... realized 1 place... initial wire length = 491 at iteration #50: temp = 4.9361, wire length = 358 at iteration #100: temp = 2.53391, wire length = 228 at iteration #150: temp = 0.611955, wire length = 124 final wire length = 99 After placement: PIOs 8 / 72 PLBs 20 / 160 BRAMs 0 / 16 place time 0.10s route... pass 1, 0 shared. After routing: span_4 23 / 6944 span_12 6 / 1440 route time 0.04s write_txt example.asc... icetime -d hx1k -mtr example.rpt example.asc // Reading input .asc file.. // Reading 1k chipdb file.. // Creating timing netlist.. // Timing estimate: 7.60 ns (131.62 MHz) icepack example.asc example.bin rm example.blif example.asc gmake: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb' /usr/bin/env -i HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work PWD="${PWD}" OSVERSION=1302001 PATH=/ccache/libexec/ccache:/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin TMPDIR=/tmp UNAME_r=13.2-RELEASE-p10 UNAME_v=FreeBSD\ 13.2-RELEASE-p10 XDG_DATA_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work XDG_CACHE_HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.cache HOME=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work TMPDIR="/tmp" PATH=/ccache/libexec/ccache:/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES PREFIX=/usr/local LOCALBASE=/usr/local CC="cc" CFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" -fstack-protector-strong " LIBS="" CXX="c++" CXXFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CCACHE_DIR="/root/.ccache" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -C /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video gmake: Entering directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video' gmake: Nothing to be done for 'all'. gmake: Leaving directory '/wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video' =========================================================================== =================================================== ===== env: USE_PACKAGE_DEPENDS_ONLY=1 USER=root UID=0 GID=0 =========================================================================== =================================================== ===== env: NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Staging for lattice-ice40-examples-hx1k-g20180310_2 ===> Generating temporary packing list install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.v /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.v install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.rpt /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.rpt install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.bin /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.bin install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.v /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.v install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.rpt /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.rpt install -m 0644 /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.bin /wrkdirs/usr/ports/devel/lattice-ice40-examples-hx1k/work/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.bin ====> Compressing man pages (compress-man) =========================================================================== =================================================== ===== env: 'PKG_NOTES=build_timestamp ports_top_git_hash ports_top_checkout_unclean port_git_hash port_checkout_unclean built_by' 'PKG_NOTE_build_timestamp=2024-03-30T08:46:46+0000' 'PKG_NOTE_ports_top_git_hash=c2c35d895e' 'PKG_NOTE_ports_top_checkout_unclean=yes' 'PKG_NOTE_port_git_hash=8d3e020ed0' 'PKG_NOTE_port_checkout_unclean=no' 'PKG_NOTE_built_by=poudriere-git-3.4.99.20240122_1' NO_DEPENDS=yes USER=root UID=0 GID=0 ===> Building packages for lattice-ice40-examples-hx1k-g20180310_2 ===> Building lattice-ice40-examples-hx1k-g20180310_2 =========================================================================== =>> Cleaning up wrkdir ===> Cleaning for lattice-ice40-examples-hx1k-g20180310_2 build of devel/lattice-ice40-examples-hx1k | lattice-ice40-examples-hx1k-g20180310_2 ended at Sat Mar 30 08:47:41 GMT 2024 build time: 00:00:55